Today, display technology is applied widely in televisions, mobile phones as well as public information display. Flat panel displays for displaying pictures are widely popularized because of the advantage of being ultra-thin and energy saving. However, in most of flat panel displays, it is required to employ a gate drive chip to output a gate scan signal so as to control the display panel to implement functions of progressive scanning and frame-by-frame refreshing, thereby image data input to the display panel can be refreshed in real time, and thus the dynamical display can be achieved.
In order to implement the progressive scanning of the display panel, multiple gate drive chips are usually arranged in the peripheral area of the display panel to input gate turn on voltages to gate lines of the display area. As shown in FIG. 1, on one side, for example, the left side, of the peripheral area of the display panel, there are two gate drive chips GD1 and GD2. The gate turn on voltage is generated by a voltage generation module DC, and is then output to the cascaded gate drive chips GD1 and GD2 which output gate scan signals to gate lines of the display area sequentially under the control of a clock control module TCON, implementing the progressive scanning of the display panel. However, since the gate turn on voltage signal is transferred to the gate drive chip GD2 via the gate drive chip GD1, in the procedure of transfer, the trace impedance of the gate turn on voltage signal on the gate drive chip GD1 is inconsistent with that of the gate turn on voltage signal on the gate drive chip GD2 due to the long wiring length, making that the gate turn on voltage, i.e. the gate scan signal, output by the gate drive chip GD1 is different from the gate scan signal output by the gate drive chip GD2. Thus, the gate turn on voltages output by different gate drive chips differ from each other, resulting that the phenomenon of horizontal two split screen occurs, and the quality of the display screen is affected.